The present invention relates to a semiconductor device and a method for fabricating the semiconductor device.
In recent years, with the increasing miniaturization of semiconductor integrated circuit devices, the distance between interconnects that connect semiconductor integrated circuit devices, and the distance between interconnects formed in semiconductor integrated circuit devices have been reduced. Due to this, a problem has emerged in that the capacitance between interconnects increases causing a reduction in signal transmission speed. In light of this, as described in pp. 213-215 in “45 nm Node Multi Level Interconnects with Porous SiOCH Dielectric k=2.5” by V. Arnal et, al. (IITC2006), methods for reducing the capacitance between interconnects by using interlayer insulating films (Low-k films) having low dielectric constants are being studied. The semiconductor device fabrication method described in the above-mentioned document will be discussed below with reference to FIG. 17.
First, as shown in FIG. 17A, an interlayer insulating film 1 is deposited on the surface of a semiconductor substrate (not shown), and then wiring grooves 2 are formed in the interlayer insulating film 1 by photolithography and by dry etching. As the interlayer insulating film 1, an interlayer insulating film having a low dielectric constant, such as a SiOC film, is employed. Thereafter, a barrier film 3 and a Cu film 4 are deposited in this order on the surface of the interlayer insulating film 1 and in the wiring grooves 2. Part of the barrier film 3 and part of the Cu film 4 protruding out from the wiring grooves 2 are then removed by performing a CMP (Chemical Mechanical Polishing) process. Consequently, lower-level interconnects 5 are formed in the wiring grooves 2.
Next, as shown in FIG. 17B, a liner insulating film 6 is deposited on the surfaces of the interlayer insulating film 1 and lower-level interconnects 5, and an interlayer insulating film 7 is deposited on the surface of the liner insulating film 6.
Subsequently, as shown in FIG. 17C, via holes 8a are formed in the liner insulating film 6 and interlayer insulating film 7 by lithography and by dry etching. Thereafter, wiring grooves 9 are formed in the interlayer insulating film 7.
Next, as shown in FIG. 17D, a barrier film 10 and a Cu film 11 are deposited in this order on the surface of the interlayer insulating film 7, in the via holes 8a, and in the wiring grooves 9. Then, part of the barrier film 10 and part of the Cu film 11 protruding out from the wiring grooves 9 are removed by performing a CMP process. Consequently, vias 8 are formed in the via holes 8a, and upper-level interconnects 12 are formed in the wiring grooves 9.
Then, as shown in FIG. 17E, a liner insulating film 13 is deposited on the surfaces of the interlayer insulating film 7 and upper-level interconnects 12, and an interlayer insulating film 14 is deposited on the surface of the liner insulating film 13. Thereafter, the surface of the interlayer insulating film 14 is planarized by performing a CMP process. This process completes the semiconductor device having the two-level interconnection structure shown in FIG. 17E. After that, repeating the process steps shown in FIGS. 17C to 17E also enables fabrication of a semiconductor device having a multilevel interconnection structure of any levels.